1. Field of the Invention
The present invention relates to a display unit or the like using an organic light emitting diode (OLED). More particularly, the present invention relates to a display unit or the like in which compensation is made for variation in the threshold voltage (Vth) of a drive transistor.
2. Discussion of the Prior Art
An OLED (also referred to as “organic EL”) is a device in which a dc voltage is applied to a fluorescent organic compound capable of being excited in an electric field to cause the compound to emit light, and which attracts attention as a next-generation display device. This OLED is a current-driven device, and a reduction in image quality results directly from variations in drive transistors for driving the OLEDs or variations in current due to degradation. In improving the image quality, it is effective to use a method of stabilizing the current output from each drive transistor by making compensation for variation in the threshold voltage (Vth), i.e., the point at which a current starts flowing through the drive transistor. OLED drive systems are broadly divided into voltage-write systems and current-write systems. Circuits for Vth compensation in each kind of drive system have been proposed.
FIGS. 8A and 8B are diagrams for explaining a method of realizing Vth compensation in a conventional voltage-write system. FIG. 8A is a circuit diagram and FIG. 8B is a timing chart. Referring to the circuit diagram of FIG. 8A relating to a voltage-write system using transistors, four FETs 201 to 204 and two capacitors 205 and 206 are used to drive an OLED 200. The FET 201 is a switch provided between a data line and the capacitor 205. The FET 202 is a transistor for driving the OLED 200. The FET 203 is a switch provided between the drain and the gate of the FET 202. The FET 204 is a switch provided between the FET 202 and the OLED 200. The capacitor 205 stores a data voltage, while the capacitor 206 stores Vth. When the FET 203 is turned on, the drain voltage and the gate voltage of the FET 202 are equal to each other. At this time, if a voltage is applied to the drain of the FET 202, the FET 202 is fully on. If no voltage is applied to the drain of the FET 202, charge on the FET 202 escapes through the drain to finally turn off the FET 203. At this time, Vth remains at the gate of the FET 203.
The operation of this circuit will be described with respect to periods with reference to FIG. 8B.
First, in a period (1), signal “Select” falls to turn on the FET 201, and AZ also falls to turn on the FET 203. In the preceding period, AZB is on and, therefore, the OLED 200 is in such a state that a current flows therethrough and the drain potential Vd of the FET 202 is sufficiently high relative to the ground potential of the OLED 200. That is, the potential Vd is sufficiently low. Thus, the gate-source voltage Vgs of the FET 202 has been shifted sufficiently largely in the minus direction, so that the FET 202 is maintained in the on state. In this state, the potential of the OLED 200 is about Vth. In this period, Vth compensation in the OLED 200 is made.
Next, in a period (2), after AZ has fallen to turn on the FET 203, AZB rises to turn off the FET 204. A current from Vdd flows round to the gate of the FET 202 to heighten the potential Vgs until Vgs=Vth. When Vgs=Vth, the FET 202 is turned off. When AZ rises to turn off the FET 203, Vth is programmed in C1 and C2.
In a period (3), when a signal of a level lower by ΔVdata than Vdd is input to a Data line, the voltages stored in the capacitors 205 and 206 are changed by capacitive division.
                                                                        V                C2                            =                              Vdd                -                Vth                                                                                                        ->                                  V                  C2                                            =                              Vdd                -                Vth                -                                                                            C1                                              C1                        +                        C2                        +                        Cg                                                              ·                    Δ                                    ⁢                                                                          ⁢                  Vdata                                                                                        (                  Equation          ⁢                                          ⁢          1                )            
In a period (4), AZB becomes on and the OLED 200 emits light. The current Ids flowing between the drain and source of the FET 202 is as shown by the following equation, which can be formed without the term Vth.Ids=α(Vgs−Vth)2=α(β×Δdata−Vdd)2  (Equation 2)
In this equation,
                    β        =                  C1                      C1            +            C2            +            Cg                                              (                  Equation          ⁢                                          ⁢          3                )            
FIGS. 9A and 9B are diagrams for explaining Vth compensation realized in a conventional current-write system. FIG. 9A is a circuit diagram and FIG. 9B is a timing chart. Referring to the circuit diagram of FIG. 9A relating to a current-write system using transistors, four FETs 211 to 214 and a capacitor 215 are used to drive an OLED 200. The FET 211 is a switch provided between a data line and the capacitor 215. The FET 212 is a transistor for driving the OLED 200. The FET 213 is a switch provided between the FET 212 and the OLED 200. The FET 214 is a switch provided between the drain and the gate of the FET 213. The capacitor 215 stores Vth.
The operation of this circuit will be described with respect to periods with reference to FIG. 9(b).
First, in a period (1), the FET 212 is turned off to shut off Vdd, thereby turning on the FETs 211 and 214. At this time, Idata flows through the FET 213. In a period (2), a voltage according to Idata is programmed in the capacitor 215. In a period (3), the FETs 211 and 214 are turned off and the FET 212 is turned on, thereby supplying Vdd to the FET 213 and to the OLED 200. At this time, current Idata is supplied to the OLED 200 according to the voltage stored in the capacitor 215.
Vth compensation has been made by the above-described systems. The above-described systems, however, require provision of two transistors connected in series (FETs 202 and 204 in the voltage-write system, and FETs 212 and 213 in the current-write system) between the power source Vdd and the OLED 200. That is, in order to detect Vth, it is necessary to connect two transistors in series and to use one of them for on/off control and the other for current control.
However, if the OLED 200 is driven by using an amorphous silicon (a-Si) thin-film transistor (TFT) for example, and if there is a need to cause a sufficiently large current to flow through the OLED 200, it is necessary that the TFT be large because the mobility in the amorphous silicon TFT is low and the current caused to flow therethrough is limited. If each of the above-described systems is realized by using amorphous silicon TFTs, the area occupied by the transistors is considerably large. On the other hand, there is a limit to the pixel size in displays. For this reason of mounting, it is difficult to use the above-described circuit requiring a certain number of large TFTs for forming a pixel.